1. Field of the Invention
The present invention relates to a so-called U interface transceiver circuit for an ISDN transmission. The present invention more specifically relates to the use of such a circuit on lines connecting base stations to a base station controller in a radiotelephony network according to the DECT standard.
2. Discussion of the Related Art
FIG. 1 schematically and partially shows a DECT telephone network. This network includes a cluster of base stations 10, each of which covers a cell 12 in which a user can correspond with the base station by radio communication. The base stations are connected to a common base station controller 14, itself connected to a central office 16.
The lines between the base stations and the base station controller introduce different transmission delays, due to the different line lengths. Further, the delay introduced by a line is likely to vary, especially according to the temperature.
When a user exits a cell 12 covered by a first base station 10, he normally enters into an adjacent cell covered by a new base station. Thus, the telephone communication must be taken over by the new base station without disturbance. However, the lines of the initial station and of the new station can introduce such different delays that they greatly disturb the communication, to the point of interrupting it.
Accordingly, base station controller 14 must know the delays introduced by each of the lines connecting it to a base station, to properly manage the transition from one line to the other.
It is desired, in such a situation, to be able to measure the different delays introduced by the lines at the level of the transceiver circuits of base station controller 14.
FIG. 2 partially and schematically shows a conventional transceiver circuit, or U interface, such as that described in European patent application 0680170 which application is incorporated herein by reference. FIG. 2 more specifically shows the elements meant for reconstructing a reception clock signal from the data received over the line.
This circuit includes a divider 20 (a counter to 192) generating a 80-kHz internal clock signal based on a 15.36-MHz signal CK. This internal clock signal forms transmission clock TxCK. This transmission clock clocks a transmission circuit 22 which forms transmission frames Tx from exiting messages MSGo. The incoming frames Rx are provided to an analog-to-digital converter 24 which is clocked by a reception clock RxCK to sample each incoming bit. The samples are provided by converter 24 to a first-in-first-out type memory (FIFO) 26 before being provided to a digital signal processor (DSP) 28. FIFO memory 26 is selected in the write mode by reception clock RxCK and selected in the read mode by internal clock TxCK. Signal processor 28 regenerates the incoming message MSGi from the samples read from FIFO memory 26.
Clock RxCK varies at the frequency of a digital sum generated by an adder 30 which receives, on a first input, the content of divider 20 and, on a second input, the content of a counter 32 containing phase information .phi.. The content of counter 32 varies modulo the division rate (192) of divider 20. Adder 30 also provides a value modulo this division rate. Signal RxCK is formed, for example, of the most significant bit MSB generated by adder 30.
With this configuration, the phase of signal RxCK with respect to signal TxCK is determined by the content of counter 32, as will be described in relation with FIG. 3.
Signal processor 28 analyzes the samples provided by converter 24 and modifies the content of counter 32 so that clock RxCK samples incoming signal Rx at the level of its maximum and minimum amplitudes. In this example, signal processor 28 modifies the content of counter 32 by a setting to the counting or downcounting mode u/d, counter 32 being clocked by clock TxCK.
Processor 28, counter 32 and adder 30 actually form a digital phase-locked loop to reconstruct the reception clock signal from incoming signal Rx.
FIG. 3 illustrates the evolution of the contents of divider 20 and of sum .SIGMA. generated by adder 30 as a function of time. The content of divider 20 varies in a saw-tooth from 0 to 191. Clock TxCK corresponds, for example, to the most significant bit of the content of divider 20. Then, it exhibits a high state when the content of divider 20 exceeds value 128.
Sum .SIGMA. generated by adder 30 also varies in a saw-tooth from 0 to 191, but is out of phase with respect to the content of divider 20 by a value corresponding to the content .phi. of counter 32. In fact, value .omega. is subtracted to the content of divider 20 to generate a phase lag of signal .SIGMA., such that sum .SIGMA. is zero when the content of divider 20 is equal to .omega.. Like signal TxCK, signal RxCK exhibits a high state when sum .SIGMA. exceeds 128.